View ZL30102QDG_8351904.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2004, zarlink semiconductor inc. all rights reserved. features ? synchronizes to clock-and-sync-pair to maintain minimal phase skew between an h.110 primary master clock and a secondary master clock ? supports telcordia gr-1244-core stratum 4 and 4e ? supports itu-t g.823 and g.824 for 2048 kbit/s and 1544 kbit/s interfaces ? supports ansi t1.403 and etsi ets 300 011 for isdn primary rate interfaces ? simple hardware control interface ? manual and automatic hitless reference switching ? accepts three input references and synchronizes to any combination of 8 khz, 1.544 mhz, 2.048 mhz, 8.192 mhz or 16.384 mhz inputs ? provides a range of clock outputs: 1.544 mhz, 2.048 mhz, 3.088 mhz, 6.312 mhz, 16.384 mhz and either 4.096 mhz and 8.192 mhz or 32.768 mhz and 65.536 mhz ? provides 5 styles of 8 khz framing pulses ? holdover frequency accuracy of 1x10 -7 ? provides lock, holdover and selectable out of range indication ? attenuates wander from 1.8 hz ? less than 0.6 ns pp jitter on all output clocks ? external master clock source: clock oscillator or crystal applications ? synchronization and timing control for multi-trunk ds1/ e1 terminal systems such as dslams, gateways and pbxs ? clock and frame pulse source for h.110 ct bus, st-bus, gci and other time division multiplex (tdm) buses july 2004 ordering information ZL30102QDG 64 pin tqfp -40 c to +85 c zl30102 t1/e1 stratum 4/4e redundant system clock synchronizer for ds1/e1 and h.110 data sheet figure 1 - functional block diagram reference monitor mode control virtual reference ieee 1149.1a tie corrector enable state machine frequency select mux tie corrector circuit mode_sel1:0 tck ref1 rst ref_sel1:0 tie_clr c1.5o c4/c65o c8/c32o c16o f4/f65o f8/f32o f16o osco osci master clock tdo ref0 tdi tms trst holdover fastlock hms lock ref_fail0 ref_fail1 dpll out_sel oor_sel c2o ref_fail2 ref2 ref2_sync sec_mstr e1 synthesizer ds1 synthesizer mux ds2 synthesizer c3o c6o
zl30102 data sheet 2 zarlink semiconductor inc. description the zl30102 ds1/e1 synchronizer cont ains a digital phase-locked loop (d pll), which provides timing and synchronization for ds1/e1 transmission equi pment deploying redundant network clocks. the zl30102 generates st-bus and other tdm clock and fram ing signals that are phase locked to one of three network references or to another system master-clock refere nce. it helps ensure system reliability by monitoring its references for frequency accuracy and stability and by ma intaining a tight phase alignment between the primary master-clock and secondary master clock output s even in the presence of high network jitter. the zl30102 is intended to be the central timing and synchronization resource for network equipment that complies with telcordia, etsi, itu-t and ansi network specifications.
zl30102 data sheet table of contents 3 zarlink semiconductor inc. 1.0 pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.0 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 reference select multiplexer (mux) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 reference monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 time interval error (tie) corrector circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4 digital phase lock loop (dpll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.5 frequency synthesizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.6 state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.7 master clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.0 control and modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1 out of range selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2 loop filter and limiter selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3 output clock and frame pulse selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4.1 freerun mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4.2 holdover mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4.3 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4.4 automatic mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.5 reference switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.5.1 manual reference switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.5.2 automatic reference switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.5.2.1 automatic reference switching - coarse reference failure . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.5.2.2 automatic reference switchi ng - reference frequency out-of-range . . . . . . . . . . . . . . . . . 24 3.6 clock redundancy support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.0 measures of performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.1 jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.2 jitter generation (int rinsic jitter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.3 jitter tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.4 jitter transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.5 frequency accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.6 holdover accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.7 pull-in range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.8 lock range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.9 phase slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.10 time interval error (tie) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.11 maximum time interval error (mtie) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.12 phase continuity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.13 lock time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.0 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.1 power supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2 master clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2.1 clock oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2.2 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.3 power up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.4 reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.5 clock redundancy system architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.0 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.1 ac and dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.2 performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
zl30102 data sheet list of figures 4 zarlink semiconductor inc. figure 1 - functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2 - pin connections (64 pin tqfp). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3 - reference monitor circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 4 - behaviour of the dis/re-qualify timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 5 - ds1 out-of-range thresholds for oor_sel=0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 6 - e1 out-of-range thresholds for oor_sel=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 7 - ref2_sync reference monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 8 - timing diagram of hitless reference switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 9 - timing diagram of hitless mode switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 10 - dpll block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 11 - mode switching in normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 12 - reference switching in normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 13 - reference selection in automatic mode (mode_sel=11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 14 - mode switching in automatic mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 15 - automatic reference switching - coarse reference failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 16 - automatic reference switching - out-of-range refere nce failure . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 17 - examples of ref2 & ref2_sync to output alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 18 - clock redundancy with two independent timing cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 19 - recommended power supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 20 - clock oscillator circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 21 - crystal oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 22 - power-up reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 23 - typical clocking architecture of an ectf h.110 system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 24 - timing parameter measurement voltage levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 25 - ref0/1/2 input timing and input to output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 26 - ref2_sync timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 27 - e1 output timing referenced to f8/f32o. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 28 - ds1 output timing referenced to f8/f32o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 29 - ds2 output timing referenced to f8/f32o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
zl30102 data sheet 5 zarlink semiconductor inc. figure 2 - pin connections (64 pin tqfp) zl30102 34 36 38 40 42 44 46 48 64 62 60 58 56 52 50 54 16 14 12 10 8 6 4 2 osco nc gnd out_sel c1.5o mode_sel1 v dd av dd ic c3o rst c6o v core lock hms trst gnd tdo tms holdover ref_fail1 tck agnd f4/f65o v dd ref0 ref2 nc ic fastlock c8/c32o nc c2o agnd av dd nc f8/f32o c4/c65o ref_sel0 18 20 22 24 26 30 32 28 c16o f16o tie_clr oor_sel sec_mstr tdi osci v core av dd av dd av dd av core av core gnd agnd agnd agnd ref_fail0 ref1 ref2_sync ic ic mode_sel0 ref_fail2 ref_sel1
zl30102 data sheet 6 zarlink semiconductor inc. 1.0 pin description pin # name description 1gnd ground. 0v 2v core positive supply voltage. +1.8 v dc nominal 3lock lock indicator (output). this output goes to a logic high when the pll is frequency locked to the selected input reference. 4 holdover holdover (output). this output goes to a logic high whenever the pll goes into holdover mode. 5 ref_fail0 reference 0 failure indicator (output). a logic high at this pin indicates that the ref0 reference frequency has exceeded the out-of-ran ge limit set by the oor_sel pin or that it is exhibiting abrupt phase or frequency changes. 6 ref_fail1 reference 1 failure indicator (output). a logic high at this pin indicates that the ref1 reference frequency has exceeded the out-of-ran ge limit set by the oor_sel pin or that it is exhibiting abrupt phase or frequency changes. 7 ref_fail2 reference 2 failure indicator (output). a logic high at this pin indicates that the ref2 reference frequency has exceeded the out-of-ran ge limit set by the oor_sel pin or that it is exhibiting abrupt phase or frequency changes. 8tdo test serial data out (output). jtag serial data is output on this pin on the falling edge of tck. this pin is held in high impedance state when jtag scan is not enabled. 9tms test mode select (input). jtag signal that controls t he state transitions of the tap controller. this pin is internally pulled up to v dd . if this pin is not used then it should be left unconnected. 10 trst test reset (input). asynchronously initializes the jtag tap controller by putting it in the test-logic-reset state. this pin should be pulsed low on power-up to ensure that the device is in the normal functional stat e. this pin is internally pulled up to v dd . if this pin is not used then it should be connected to gnd. 11 tck test clock (input): provides the clock to the jtag test logi c. if this pin is not used then it should be pulled down to gnd. 12 v core positive supply voltage. +1.8 v dc nominal 13 gnd ground. 0v 14 av core positive analog supply voltage. +1.8 v dc nominal 15 tdi test serial data in (input). jtag serial test instructions and data are shifted in on this pin. this pin is internally pulled up to v dd . if this pin is not used then it should be left unconnected. 16 hms hitless mode switching (input). the hms input controls phase accumulation during the transition from holdover or freerun mode to normal mode on the same reference. a logic low at this pin will cause the zl30102 to main tain the delay stored in the tie corrector circuit when it transitions from holdover or freerun mode to normal mode. a logic high on this pin will cause the zl30102 to measure a new delay for its tie corrector circuit thereby minimizing the output phase movement when it tr ansitions from holdover or freerun mode to normal mode. 17 mode_sel0 mode select 0 (input). this input combined with mode_ sel1 determines the mode of operation, see table 4 on page 19. 18 mode_sel1 mode select 1 (input). see mode_sel0 pin description.
zl30102 data sheet 7 zarlink semiconductor inc. 19 rst reset (input). a logic low at this input resets the device. on power up, the rst pin must be held low for a minimum of 300 ns after the power supply pins have reached the minimum supply voltage. when the rst pi n goes high, the device will transition into a reset state for 3 ms. in the reset state all outputs will be forced into high impedance. 20 osco oscillator master clock (output). for crystal operation, a 20 mhz crystal is connected from this pin to osci. this output is not suitable for driving other devices. for clock oscillator operation, this pi n must be left unconnected. 21 osci oscillator master clock (input). for crystal operation, a 20 mhz crystal is connected from this pin to osco. for clock oscillator operation, this pin must be connected to a clock source. 22 ic internal connection. leave unconnected. 23 gnd ground. 0v 24 nc no internal bonding connection. leave unconnected. 25 v dd positive supply voltage. +3.3 v dc nominal 26 out_sel output selection (input). this input selects the signals on the combined output clock and frame pulse pins, see table 3 on page 18. 27 ic internal connection. connect this pin to ground. 28 ic internal connection. connect this pin to ground. 29 av dd positive analog supply voltage. +3.3 v dc nominal 30 c6o clock 6.312 mhz (output). this output is used in ds2 applications. 31 c3o clock 3.088 mhz (output). this output is used in ds1 applications. 32 c1.5o clock 1.544 mhz (output). this output is used in ds1 applications. this clock output pad includes a schmitt input which serves as a pll feedback path; proper transmission-line termi nation should be applied to maintain reflections below schmitt trigger levels. 33 agnd analog ground. 0v 34 agnd analog ground. 0v 35 av core positive analog supply voltage. +1.8 v dc nominal 36 av dd positive analog supply voltage. +3.3 v dc nominal 37 av dd positive analog supply voltage. +3.3 v dc nominal 38 nc no internal bonding connection. leave unconnected. 39 nc no internal bonding connection. leave unconnected. 40 agnd analog ground. 0v 41 agnd analog ground. 0v 42 c4 /c65o clock 4.096 mhz or 65.536 mhz (output). this output is used for st-bus operation at 2.048 mbit/s, 4.096 mbit/s or 65.536 mhz (s t-bus 65.536 mbit/s). the output frequency is selected via the out_sel pin, see table 3 on page 18. pin # name description
zl30102 data sheet 8 zarlink semiconductor inc. 43 c8/c32o clock 8.192 mhz or 32.768 mhz (output). this output is used for st-bus and gci operation at 8.192 mb/s or for operation with a 32.768 mhz clock. the output frequency is selected via the out_sel pin, see table 3 on page 18. in c8 mode, this clock output pad uses an included schmitt input as a pll feedback path; proper transmission-line termination should be applied to maintain reflections below schmitt trigger levels. 44 av dd positive analog supply voltage. +3.3 v dc nominal 45 av dd positive analog supply voltage. +3.3 v dc nominal 46 c2o clock 2.048 mhz (output). this output is used for standard e1 interface timing and for st-bus operation at 2.048 mbit/s. this clock output pad includes a schmitt input which serves as a pll feedback path; proper transmission-line termi nation should be applied to maintain reflections below schmitt trigger levels. 47 c16o clock 16.384 mhz (output). this output is used for st-bus operation with a 16.384 mhz clock. this clock output pad includes a schmitt input which serves as a pll feedback path; proper transmission-line termi nation should be applied to maintain reflections below schmitt trigger levels. 48 f8/f32o frame pulse (output). this is an 8 khz 122 ns active high framing pulse or it is an 8 khz 31 ns active high framing pulse, which marks the beginning of a frame. the pulse width is selected via the out_sel pin, see table 3 on page 18. 49 f4 /f65o frame pulse st-bus 2.048 mbit/s or st-bus at 65.536 mhz clock (output). this output is an 8 khz 244 ns active low frami ng pulse which marks the beginning of an st- bus frame. this is typically used for st-bus operation at 2.048 mbit/s and 4.096 mbit/s. or this output is an 8 khz 15 ns active lo w framing pulse, typically used for st-bus operation with a clock rate of 65.536 mhz. t he pulse width is selected via the out_sel pin, see table 3 on page 18. 50 f16o frame pulse st-bus 8. 192 mbit/s (output). this is an 8 khz 61 ns active low framing pulse, which marks the beginning of an st-bus frame. this is typically used for st-bus operation at 8.192 mbit/s. 51 agnd analog ground. 0v 52 ic internal connection. connect this pin to ground. 53 ref_sel0 reference select 0 (input/output). in the manual mode of operation, ref_sel0 is an input. as an input ref_sel0 combined with ref_sel1 selects the reference input that is used for synchronization, see table 6 on page 22. in the automatic mode of operation, refsel0 is an output indicating which of the input references is the being selected. this pin is internally pulled down to gnd. 54 ref_sel1 reference select 1 (input/output) . see ref_sel0 pin description. 55 ref0 reference (input). this is one of three (ref0, ref1 and ref2) input reference sources used for synchronization. one of five possible frequencies may be used: 8 khz, 1.544 mhz, 2.048 mhz, 8.192 mhz or 16.384 mhz. this pin is internally pulled down to gnd. 56 ref1 reference (input). see ref0 pin description. 57 ref2 reference (input). see ref0 pin description. pin # name description
zl30102 data sheet 9 zarlink semiconductor inc. 58 ref2_sync ref2 synchronization frame pulse (input). this is the 8 khz frame pulse synchronization input associated with the ref2 reference. while the pll is locked to the ref2 input reference the output (multi) frame pu lses are synchronized to this input. this pin is internally pulled down to gnd. 59 sec_mstr secondary master mode selection (input). a logic low at this pin selects the primary master mode of operation with 1.8 hz dpll l oop filter bandwidth. a logic high selects secondary master mode which forces the pll to clear its tie corrector circuit and lock to the selected reference using a high bandwidt h loop filter and a phase slope limiting of 9.5 ms/s. 60 oor_sel out of range selection (input). this input selects the frequency out of range limits of the reference inputs, see table 1 on page 18. 61 v dd positive supply voltage. +3.3 v dc nominal 62 nc no internal bonding connection. leave unconnected. 63 tie_clr tie circuit reset (input). a logic low at this input resets the time interval error (tie) correction circuit resulting in a realignment of input phase with output phase. 64 fastlock fast lock (input). set temporarily high to allow the zl30102 to quickly lock to the input reference (one second locking time). pin # name description
zl30102 data sheet 10 zarlink semiconductor inc. 2.0 functional description the zl30102 is an sdh/pdh synchronizer for redundant system clocks, providing timing and synchronization signals to interface circuits for the following types of primary rate digital transmission links, see table 1: ? ds1 compliant with ansi t1.403 and telcordia gr-1244-core stratum 4/4e ? e1 compliant with itu-t g.703 and etsi ets 300 011 figure 1 is a functional block diagram of the zl 30102 which is described in the following sections. 2.1 reference sele ct multiplexer (mux) the zl30102 accepts three simultaneous reference input signals and operates on thei r rising edges. one of them, the primary reference (ref0), the secondary reference (ref1) or the tertiary reference (ref2) signal is selected as input to the tie corrector circuit based on the reference selection (ref_sel1:0) inputs. the use of the combined ref2 and ref2_sync inputs allows for a very accurate phase alignment of the output frame pulses to the 8 khz frame pulse supplied to the re f2_sync input. this feature supports the implementation of primary and secondary master system clocks in h.110 systems. 2.2 reference monitor the input references are monitored by three independent reference monitor blocks, one for each reference. the block diagram of a single reference monitor is shown in figure 3. for each reference clock, the frequency is detected and the clock is continuously monitored for thr ee independent criteria that indicate abnormal behavior of the reference signal, for example; long term drift from it s nominal frequency or excessive jitter. to ensure proper operation of the reference monitor circuit, the minimu m input pulse width restriction of 15 nsec must be observed. ? reference frequency detector (rfd) : this detector determines whether the frequency of the reference clock is 8 khz, 1.544 mhz, 2.048 mhz 8.192 mhz or 16.384 mhz and provides this information to the various monitor circuits and the phase detector circuit of the dpll. ? precise frequency monitor (pfm) : this circuit determines whether the frequency of the reference clock is within the selected accuracy range, see table 1. ? coarse frequency monitor (cfm) : this circuit monitors the reference frequency over intervals of approximately 30 s to quickly detect large frequency changes. ? single cycle monitor (scm) : this detector checks the period of a single clock cycle to detect large phase hits or the complete loss of the clock.
zl30102 data sheet 11 zarlink semiconductor inc. figure 3 - reference monitor circuit exceeding the thresholds of any of the monitors forces the corresponding ref_fail pin to go high. the single cycle and coarse frequency failure flags force the dpll into holdover mode and feed a timer that disqualifies the reference input signal when the failures are present for mo re than 2.5 s. the single cycle and coarse frequency failures must be absent for 10 s to let the timer re-qualify th e input reference signal as valid. multiple failures of less than 2.5 s each have an accumulative effect and will disqua lify the reference eventually. this is illustrated in figure 4 where ref0 experiences disruptions while ref1 is stable. figure 4 - behaviour of the dis/re-qualify timer reference frequency detector single cycle monitor precise frequency monitor coarse frequency monitor dis/re-qualify timer ref0 / ref1 / ref2 or or or ref_oor = reference out of range. ref_dis= reference disrupted. both are internal signals. reference select state machine ref_sel1:0 ref_oor mode select state machine holdover ref_dis ref_fail0 / ref_fail1 / ref_fail2 2.5 s 10 s ref0 dis/re-qualify scm or cfm failure ref_fail0 holdover ref_oor0 (internal signal) ref1 ref0 ref1 ref0 ref_sel timer on ref0 scm or cfm failure
zl30102 data sheet 12 zarlink semiconductor inc. when the incoming signal returns to normal (ref_fail= 0), the dpll returns to normal mode with the output signal locked to the input signal. each of the monitors has a build-in hysteresis to prevent flickering of the ref_fail status pin at the thres hold boundaries. the precise frequency m onitor and the timer do not affect the mode (holdover/normal) of the dpll. if the device is set to automatic mode (mode_sel1:0=11 ), then the state machine does not immediately switch to another reference. if the single cycle and/or coarse frequency failures persist for more than 2.5 s or the precise frequency monitor detects a failure, then the state machine will switch to another valid refe rence if that is available. if there no other reference availabl e, it stays in holdover mode. the precise frequency monitor?s failure thresholds ar e selected with the oor_sel input based on the zl30102 applications, table 1. figure 5 and figur e 6 show the out of range limits for va rious master clock accuracies. it will take the precise frequency monitor up to 10 s to qualify or disqualify the input reference. figure 5 - ds1 out-of-range thresholds for oor_sel=0 figure 6 - e1 out-of-range thresholds for oor_sel=1 in addition to the monitoring of the ref2 reference signal the companion ref2_sync input signal is also monitored for failure (see figure 7). c20 clock accuracy 0 ppm +32 ppm -32 ppm 0 51 83 64 32 32 -32 -96 -75 -50 0 -25 25 75 frequency offset [ppm] out of range out of range out of range in range in range in range c20 50 -64 -83 115 96 -32 -51 -115 c20 c20 100 -100 c20: 20 mhz master oscillator clock 0 ppm +50 ppm -50 ppm 0 50 130 100 50 80 -50 -150 -150 -100 0 -50 50 150 frequency offset [ppm] out of range out of range out of range in range in range in range c20 100 -100 -130 180 150 -50 -80 -180 c20 c20 -200 200 c20: 20 mhz master oscillator clock c20 clock accuracy
zl30102 data sheet 13 zarlink semiconductor inc. sync ratio monitor (srm) : this monitor detects if the ref2_sync sign al is an 8 khz signal. it also checks the number of ref2 reference clock cycles in a single ref2_sync frame pulse peri od to determine the integrity of the ref2_sync signal, for example there mu st be exactly 256 clock cycles of a 2.048 mhz ref2 reference clock in a single ref2_sync 8 khz frame pulse period to validat e the ref2_sync signal. if the ref2 and ref2_sync inputs are selected for synchronization and the sync rati o monitor detects a failure, the dpll will abandon the mechanism of aligning the output frame pulse to the ref2_sync pulse. instead only t he ref2 reference will be used for synchronization. figure 7 - ref2_sync reference monitor 2.3 time interval error (tie) corrector circuit the tie circuit eliminates phase transi ents on the output clock that may occu r during reference switching or the recovery from holdover mode to normal mode. on recovery from holdover mode (dependent on the hms pi n) or when switching to another reference input, the tie corrector circuit measures the phase delay between the current phase (feedback si gnal) and the phase of the selected reference signal. this delay value is stored in th e tie corrector circuit. this circuit creates a new virtual reference signal that is at the same phase position as t he feedback signal. by using th e virtual reference, the pll minimizes the phase transient it experiences when it reco vers from holdover mode. the delay value can be reset by setting th e tie corrector circuit clear pin (tie_clr ) low for at least 15 ns. this results in a phase alignment between the input reference si gnal and the output clocks and frame pulses as shown in figure 25. the speed of the phase alignment correction is limited by the selected loop filter bandwidth and the phase slope limit (see table 2). convergence is always in the direction of least phase travel. tie_clr can be kept low continuously; in that case the output clocks will always align with the selected input re ference. this is illustrated in figure 8. sync reference monitor circuit to dpll ref2_sync ref2 frequency ref2
zl30102 data sheet 14 zarlink semiconductor inc. figure 8 - timing diagram of hitless reference switching the hitless mode switching (hms) pin enables phase hitl ess returns from freerun and holdover modes to normal mode in a single reference operation. a logic low at the hms input disables the tie ci rcuit updating the delay value thereby forcing the output of t he pll to gradually move back to the original point before it went into holdover mode. (see figure 9). this prevents accumulation of phase in network elements. a logic high (hms=1) enables the tie circuit to update its delay value thereby preventing a la rge output phase movement after return to normal mode. this causes accumulation of phase in network elements. in both cases the pll?s output can be aligned with the input reference by setting tie_clr low. regardless of the hms pin state, reference switching in the zl30102 is always hitless unless tie_clr is kept low continuously. locked to ref1 ref0 output clock tie_clr = 1 tie_clr = 0 ref1 ref0 output clock ref1 locked to ref1 ref0 output clock ref1 ref0 output clock ref1 locked to ref0 locked to ref0
zl30102 data sheet 15 zarlink semiconductor inc. figure 9 - timing diagram of hitless mode switching examples: hms=1 : when ten normal to holdover to normal mode trans itions occur and in each case the holdover mode was entered for 2 seconds then the accumulated phase change (mtie) could be as large as 2.13 s. - phase holdover_drift = 0.1 ppm x 2 s = 200 ns - phase mode_change = 0 ns + 13 ns = 13 ns - phase 10 changes = 10 x (200 ns + 13 ns) = 2.13 s ref phase drift in holdover mode hms = 0 normal mode return to normal mode ref output clock ref output clock ref output clock phase drift in holdover mode normal mode return to normal mode output clock ref output clock ref output clock hms = 1 tie_clr =0 ref output clock tie_clr =0 ref output clock
zl30102 data sheet 16 zarlink semiconductor inc. where: - 0.1 ppm is the accuracy of the holdover mode - 0 ns is the maximum phase discontinuity in the tran sition from the normal mode to the holdover mode - 13 ns is the maximum phase discontinuity in the tran sition from the holdover mode to the normal mode when a new tie corrector value is calculated hms=0 : when the same ten normal to holdover to normal mode changes occur and in each case holdover mode was entered for 2 seconds, then the overall mtie would be 20 ns. as the delay value for the tie corrector circuit is not updated, there is no 13 ns measurement error at this point. the phase can still drift for 20 ns when the pll is in holdover mode but when the pll enters normal mode agai n, the phase moves back to the original point so the phase is not accumulated. 2.4 digital phase lock loop (dpll) the dpll of the zl30102 consists of a phase detector, a limite r, a loop filter and a digitally controlled oscillator as shown in figure 10. the data path from the phase detector to the limiter is tapped and routed to the lock indicator that provides a lock indication which is output at the lock pin. figure 10 - dpll block diagram phase detector - the phase detector compares t he virtual reference signal from th e tie corrector circuit with the feedback signal and provides an error signal corresponding to the phase differ ence between the two. this error signal is passed to the limiter circuit. limiter - the limiter receives the error signal from the phas e detector and ensures that the dpll responds to all input transient conditions with a ma ximum output phase slope compliant wi th the applicable standards. the phase slope limit is dependent on the sec_mstr pin and is listed in table 2. loop filter - the loop filter is similar to a first order low pass filter with a bandwidth of 1.8 hz suitable to provide primary master timing. when secondary master mode is selected (sec_m str=1), the filter bandwidth is set to 922 hz. for stability reasons, the loop filter bandwidth for 8 khz reference inputs is limited to a maximum of 58 hz. state select from control state machine feedback signal from frequency select mux dpll reference to frequency synthesizer virtual reference from tie corrector circuit limiter loop filter digitally controlled oscillator phase detector ref2_sync frame pulse lock detector lock feedback frame pulse; f8o or f2ko
zl30102 data sheet 17 zarlink semiconductor inc. digitally controlled oscillator (dco) - the dco receives the limited and filt ered signal from the loop filter, and based on its value, generates a corresponding digital output signal. the synchroniza tion method of the dco is dependent on the state of the zl30102. in normal mode, the dco provides an output signal which is frequency and phase locked to the selected input reference signal. in holdover mode, the dco is free running at a frequenc y equal to the frequency that the dco was generating in normal mode. the frequency in holdover mode is calcul ated from frequency samples stored 26 ms to 52 ms before the zl30102 entered holdover mode. this ensures that th e coarse frequency monitor and the single cycle monitor have time to disqualify a bad reference before it corrupts the holdover frequency. in freerun mode, the dco is free running with an accu racy equal to the accuracy of the osci 20 mhz source. lock indicator - the lock detector monitors if the output value of the phase detector is within the phase-lock- window for a certain time. the select ed phase-lock-window guarantees the stabl e operation of the lock pin with maximum network jitter and wander on the reference input. if the dpll goes into holdover mode (auto or manual), the lock pin will initially stay high for 1 s in primary master mode. in secondary ma ster mode, lock remains high for 0.1 s. if at that point the dpll is still in holdover mo de, the lock pin will go low; subsequently the lock pin will not return high for at least the full lock-time durat ion. in freerun mode the lock pin will go low immediately. 2.5 frequency synthesizers the output of the dco is used by the frequency synthesizers to generate the ou tput clocks and frame pulses which are synchronized to one of three reference inputs (ref0, ref1 or ref2). the frequency synthesizer uses digital techniques to generate output clocks and advanced noise sh aping techniques to minimize the output jitter. the clock and frame pulse outputs have limited driving capabi lity and should be buffered when driving high capacitance loads. 2.6 state machine as shown in figure 1, the state machine controls the tie corrector circuit and the dpll. the control of the zl30102 is based on the inputs mode_sel1:0, ref_sel1:0 and hms. 2.7 master clock the zl30102 can use either a clock or crystal as t he master timing source. fo r recommended master timing circuits, see the applications - master clock section.
zl30102 data sheet 18 zarlink semiconductor inc. 3.0 control and modes of operation 3.1 out of range selection the out of range limits for the precise frequency monitor in the 3 reference monitor blocks are selected through the oor_sel pin, see table 1. 3.2 loop filter and limiter selection the loop filter and limiter settings are selected throug h the sec_mstr pin, see table 2. the maximum loop filter bandwidth is also dependent on the frequency of the currently selected reference (ref0/1/2). 3.3 output clock a nd frame pulse selection the output of the dco is used by the frequency synthesizers to generate the ou tput clocks and frame pulses which are synchronized to one of three reference inputs (ref0, ref1 or ref2). these signals are available in two groups controlled by the out_sel pin, see table 3. 3.4 modes of operation the zl30102 has three possible manual modes of operat ion; normal, holdover and freerun. these modes are selected with mode select pins mode_sel1 and mode_sel0 as is shown in table 4. transitioning from one mode to the other is controlled by an external controll er. the zl30102 can be configured to automatically select a valid input reference under control of its internal state machine by setting mode_sel1:0 = 11. in this mode of operation, a state machine controls selection of references (ref0 or ref1) used for synchronization. oor_sel application applicable standard out of range limits 0 ds1 ansi t1.403 telcordia gr-1244-core stratum 4/4e 64 - 83 ppm 1e1 itu-t g.703 etsi ets 300 011 100 - 130 ppm table 1 - out of range limits selection sec_mstr detected ref frequency loop filter bandwidth phase slope limiting 0 any 1.8 hz 61 /s 1 8 khz 58 hz 9.5 ms /s 1.544 mhz, 2.048 mhz, 8.192 mhz, 16.384 mhz 922 hz 9.5 ms /s table 2 - loop filter and limiter settings out_sel generated clocks generated frame pulses 0c2o, c4o , c8o, c16o f4o , f8o, f16o 1 c2o, c16o, c32, c65o f16o , f32o, f65o table 3 - clock and frame pulse selection with out_sel pin
zl30102 data sheet 19 zarlink semiconductor inc. 3.4.1 freerun mode freerun mode is typically used when an independent clock s ource is required, or i mmediately following system power-up before network synchronization is achieved. in freerun mode, the zl30102 provides timing and sync hronization signals which are based on the master clock frequency (supplied to osci pin) only, and are not synchronized to the reference input signals. the accuracy of the output clock is equal to t he accuracy of the master clock (osci). so if a 32 ppm output clock is required, the master clock must also be 32 ppm. see applications - section 5.2, ?master clock?. 3.4.2 holdover mode holdover mode is typically used for short durations wh ile network synchronization is temporarily disrupted. in holdover mode, the zl30102 provides timing and synchr onization signals, which are not locked to an external reference signal, but are based on st orage techniques. the storage value is determined while the device is in normal mode and locked to an external reference signal. when in normal mode, and locked to the input refere nce signal, a numerical value corresponding to the zl30102 output reference frequency is stored al ternately in two memory locations ev ery 26 ms. when the device is switched into holdover mode, the value in memory from between 26 ms and 52 ms is used to set the output frequency of the device. the frequency accuracy of holdover mode is 0.1 ppm. two factors affect the accuracy of holdover mode. one is drift on the master clock while in holdover mode, drift on the master clock directly affects the holdover mode accu racy. note that the absolute master clock (osci) accuracy does not affect holdover accuracy, only the change in osci accuracy while in holdover. for example, a 32 ppm master clock may have a temperature coefficient of 0.1 ppm per c. so a 10 c change in temperature, while the zl30102 is in holdover mode may result in an addition al offset (over the 0.1 ppm) in frequency accuracy of 1 ppm. which is much greater than the 0.1 ppm of the zl30102. the other fact or affecting the accuracy is large jitter on the reference input prior to the mode switch. mode_sel1 mode_sel0 mode 0 0 normal (with automatic holdover) 0 1 holdover 10 freerun 1 1 automatic (normal with automatic holdover and automatic reference switching) table 4 - operating modes
zl30102 data sheet 20 zarlink semiconductor inc. 3.4.3 normal mode normal mode is typically used when a system clock sour ce, synchronized to the network is required. in normal mode, the zl30102 provides timing (c1.5o, c2o, c4o , c8o, c16o, c19o, c32 and c65o ) and frame synchronization (f2ko, f4o , f8o, f16o , f32o and f65o ) signals, which are synchronized to one of three reference inputs (ref0, ref1 or ref2). the input reference signal may have a nominal frequency of 8 khz, 1.544 mhz, 2.048 mhz, 8.192 mhz or 16.384 mhz. t he frequency of the reference inputs are automatically detected by the reference monitors. when the zl30102 comes out of reset while normal mode is selected by its mode_sel pins then it will initially go into holdover mode and generate clocks with the accuracy of its freerunning local oscillator (see figure 11). if the zl30102 determines that its selected reference is disrupt ed (see figure 3), it will remain in holdover until the selected reference is no longer disrupted or the external c ontroller selects another refer ence that is not disrupted. if the zl30102 determines that its selected reference is not di srupted (see figure 3) then the state machine will cause the dpll to recover from holdover via one of two paths depending on the logic level at the hms pin. if hms=0 then the zl30102 will transition directly to normal mode and it will align its output signals with its selected input reference (see figure 9). if hms=1 then the zl30102 will transition to normal mode via the tie correction state and the phase difference betw een the output signal s and the selected input re ference will be maintained. when the zl30102 is operating in normal mode, if it determ ines that its selected refe rence is disrupted (figure 3) then its state machine will cause it to automatically go to holdover mode. when the zl30102 determines that its selected reference is not disrupted then the state machine will cause the dpll to recover from holdover via one of two paths depending on the logic level at the hms pin (see figure 11). if hms=0 then t he zl30102 will transition directly to normal mode and it will align its output signals with its input reference (see fi gure 9). if hms=1 then the zl30102 will transition to normal mode via the tie corr ection state and the phase difference between the output signals and the input refe rence will be maintained. if the reference selection changes because the value of the ref_sel1:0 pins changes or because the reference selection state machine selected a different reference input, the zl30102 goes into holdover mode and returns to normal mode through the tie correction state regardless of the logi c value on hms pin. zl30102 provides a fast lock pin (fastlock), which, when set high enables the pll to lock to an incoming reference within approximately 1 s. figure 11 - mode switching in normal mode ref_dis=1: current selected reference disrupted (see figure 3). ref_dis is an internal signal. ref_ch= 1: reference change, a transition in the reference selection (see figure 13) or a change in the ref_sel pins. ref_ch is an internal signal. tie correction (holdover=1) holdover (holdover=1) ref_dis=0 ref_ch=1 ref_dis=0 and ref_dis=1 (ref_dis=0 and hms=1) or ref_ch=1 ref_dis=1 rst ref_ch=0 and hms=0 normal (holdover=0)
zl30102 data sheet 21 zarlink semiconductor inc. 3.4.4 automatic mode the automatic mode combines the functionality of the norm al mode (automatic holdover ) with automatic reference switching. the automatic reference switching is described in more detail in section 3.5.2, ?automatic reference switching?. 3.5 reference switching 3.5.1 manual reference switching in the manual modes of operation (mode_sel1:0 11) the active reference input (ref0, ref1 or ref2) is selected by the ref_sel1 and ref_sel0 pins as shown in table 5. when the logic val ue of the ref_sel pins is changed when the dpll is in normal mode, the zl3 0102 will perform a hitless reference switch. when the ref_sel inputs are used in normal mode to force a change from the currently selected reference to another reference, the action of the lock output will d epend on the relative frequency and phase offset of the old and new references. where the new reference has enough fr equency offset and/or tie-corrected phase offset to force the output outside the phase-lock-window, the lock ou tput will de-assert, the lock-qualify timer is reset, and lock will stay de-asserted for the full lock-time durat ion. where the new referenc e is close enough in frequency and tie-corrected phase for the output to stay within th e phase-lock-window, the lock output will remain asserted through the referenc e-switch process. figure 12 - reference sw itching in normal mode 3.5.2 automatic reference switching in the automatic mode of operation (mode_sel1:0 = 11), the zl30102 automatically selects a reference input that is not out-of-range (ref_oor=0, see figure 3). the state machine can only select ref0 or ref1; ref2 cannot be selected in the automatic mode (see figure 13). ref_sel1 ref_sel0 input reference selected 00 ref0 01 ref1 10 ref2 11 ref2 table 5 - manual reference selection ref1 ref0 ref_sel lock lock time note: lock pin behaviour depends on phase and frequency offset of ref1.
zl30102 data sheet 22 zarlink semiconductor inc. if the current reference (ref0 or ref1) used for synchron ization fails, the state machine will switch to the other reference. if both references fail then the zl30102 enters the holdover mode wi thout switching to another reference. when the zl30102 comes out of reset or wh en ref2 is the current reference when the zl30102 is put in the automatic mode, then ref0 has priority over re f1. otherwise there is no preference for ref0 or ref1 which is referred to as non-revertive reference selection. figure 13 - reference selection in automatic mode (mode_sel=11) in the automatic mode of operation, both pins ref_sel1 and ref_sel0 are configured as outputs. the logic level on the ref_sel0 output indicates the cu rrent input reference being selected for synchronization (see table 6). ref_sel1 (output pin) ref_sel0 (output pin) input reference 00 ref0 01 ref1 table 6 - the reference selection pins in the automatic mode (mode_sel=11) ref0 reference ref1 reference ref_oor0=1 && ref_oor1=0 rst && ref_oor0=0 rst && ref_oor0=1 && ref_oor1=0 ref_oor0=0 && ref_oor1=1 ref2 reference ref_oor0=1 && ref_oor1=0 ref_oor0=0 ref_oor = reference out of range, see figure 3. this is an internal signal.
zl30102 data sheet 23 zarlink semiconductor inc. the mode selection state machine behaves differently in automatic mode in that when both reference ref0 and reference ref1 are out of range (ref_oor=1), the state ma chine will select the holdover state. in normal mode the reference out of range (ref_oor) status is ignored by the state machin e. this is illustrated in figure 14. figure 14 - mode switching in automatic mode 3.5.2.1 automatic reference sw itching - coarse reference failure when the currently-active input reference in automatic mode fails in a coarse manner, the ref_dis internal signal places the device in holdover, with the holdover pin and the ref_fail pin asserted. this can occur through triggering the single cycle monitor, or the coarse frequency monitor, in the reference monitor block. if the reference does not correct itself within the lock-disqualif y duration (1 second) the lock pin is de-asserted. if the reference does not correct itself within the reference-di squalify duration (2.5 seconds) the holdover pin is de- asserted and the ref_sel outputs indicate that the device has switched to the other reference. the lock pin remains de-asserted for the full lock-t ime duration, regardless of the phase and frequency offset of the old and new references. figure 15 illustrates this process. if the reference corrects itself within the lock-disqualif y duration (< 1 second) the ho ldover pin is de-asserted, and the ref_fail pin is de-asserted. the lock pin rema ins asserted. no reference switching takes place, and the ref_sel outputs indicate t hat the device has remained locked to the old reference. if the reference does not correct itself within the lock-disqua lify duration (1 second), but does correct itself within the reference-disqualify duration (< 2.5 seconds) the holdo ver pin is de-asserted, the ref_fail pin is de-asserted, and the ref_sel outputs indicate that the device has remained locked to the old reference. however the lock pin is de-asserted, the lock-qualify ti mer is reset, and the lock pin remain s de-asserted for the full lock-time duration. see 6.2, ?performance characteri stics? on page 43 for lock-time duration. ref_dis=1: current selected reference disrupted (see figure 3). ref_dis is an internal signal. ref_oor=1: current selected reference out of range (see figure 3). ref_oor is an internal signal. ref_ch= 1: reference change, a transition in the reference selection (see figure 13). ref_ch is an internal signal. tie correction (holdover=1) holdover (holdover=1) ref_dis=0 ref_ch=1 ref_dis=1 (ref_dis=0 and ref_oor=0 and hms=1) rst normal (holdover=0) and ref_oor=0 or ref_oor=1 or ref_ch=1 ref_dis=0 and ref_oor=0 and ref_ch=0 and hms=0
zl30102 data sheet 24 zarlink semiconductor inc. figure 15 - automatic reference switching - coarse reference failure 3.5.2.2 automatic reference switching - reference frequency out-of-range when the currently-active input refe rence in automatic mode fails through a subtle frequency offset, the ref_fail output is asserted as soon as the precise frequency monitor indicates an out-of-range reference (10 to 20 seconds). the holdover output is briefly asserted (approxim ately three reference input cycles) and the ref_sel outputs indicate that the device has switched to the other reference. where the new reference is close enough in frequency and tie-corrected phase for the output to stay within the phase-lock-window, the lock output will remain asserted through the reference-sw itch process. where the new re ference has enough frequency offset and/or tie-corrected phase offset to force the output outside t he phase-lock-window, the lock output will de- assert, the lock-qualify timer is reset, and lock will st ay de-asserted for the full lock-time durat ion. figure 16 illustrates this process. 2.5 s 10 s ref0 ref_fail0 holdover ref_oor0 (internal signal) ref1 ref0 ref_sel scm or cfm failure lock 1 s lock time ref_dis0 (internal signal) note: this scenario is based on ref1 remaining good throughout the duration.
zl30102 data sheet 25 zarlink semiconductor inc. figure 16 - automatic reference switching - out-of-range reference failure 3.6 clock redundancy support in general, clock redundancy implies that the redundant ti ming card dpll tracks t he output clock and/or frame pulse of the active timing card dpll. in case that the ac tive timing card fails, the devi ces that use the active clock and/or frame pulse must be able to switch to the r edundant clock and/or frame pulse without experiencing disruptions. therefore the redundant signal s must closely track the active si gnals. the zl30102 supports this kind of clock redundancy in various ways; ? lock only to the active clock. the zl30102 uses the 922 hz loop filter bandwidth to closely track the active clock, even in the presence of jitter on the active clo ck. however the active and redundant frame pulse may not be aligned. ? lock to the active frame pulse. both the redundant cloc k and frame pulse will be aligned with the active clock and frame pulse. however the zl30102 loop filter bandwidth is limited to 58 hz for an 8 khz frame pulse. therefore the redundant clock and frame pulse will no t track the active frame pulse as closely in the presence of jitter on the active frame pulse as with a 922 hz loop filter bandwidth. ? lock to both the active clock and associated frame pulse. the zl30102 uses the 922 hz loop filter bandwidth and thereby track the active clock and frame pu lse in the presence of jitter on the active signals. it will also align the redundant frame pulse with the active frame pulse. the method of clock redundancy shown in figure 18 is that the redundant timing card is frequency and phase locked to the active clock and frame pulse. the redundant card is configured as secondary master (sec_mstr=1) and continuously adjusts the phase of its output clocks and fr ame pulses to match that of the active clock and frame pulse. in this mode of operation, the bandwidth of the redundant timing card?s dpll is much larger than that of the active timing card?s dpll, 922 hz vers us 1.8 hz. therefore the redundant clocks and frame pulses will track the 10 to 20 s ref0 ref_fail0 holdover ref_oor0 (internal signal) ref1 ref0 ref_sel frequency precision failure lock note: this scenario is based on ref1 remaining good throughout the duration. lock time lock pin behaviour depends on phase and frequency offset of ref1.
zl30102 data sheet 26 zarlink semiconductor inc. active clock and frame pulse closely even in the presence of the maximum tolerable input jitter and wander on the active timing card?s reference input. the method of synchronization using ref2 and ref2_sync is enabled as soon as a valid 8 khz frame pulse is detected on the ref2_sync input. the ref2_sync pulse must be generated from the clock that is present on the ref2 input. the zl30102 checks the number of ref2 cycles in the ref2_sync period. if this is not the nominal number of cycles, the ref2_sync pulse is consider ed invalid. for example, if ref2 is a 8.192 mhz clock and ref2_sync is a 8 khz frame pulse, then there must be exactly 1024 ref2 cycles in a ref2_sync period. if a valid ref2_sync pulse is detected, the zl30102 will align the rising edges of the ref2 clock and the corresponding output clock such that t he rising edge of the f8o/f32o output frame pulse is aligned with the frame boundary indicated by the ref2_sync signal. the rising edges of the ref2 and the corresponding output clock that are aligned, are t he ones that lag the rising edges of the ref2_sync and the f8o pulses respectively. this is illustrated in figure 17. many combinations of th e zl30102 clock and frame pulse outputs can be used as ref2 and ref2_sync inputs. in general, the active low frame pulses f4o , f16o and f65o would be inverted first before used as a ref2_sync input. figure 17 - examples of ref2 & ref2_sync to output alignment ref2 = c8o ref2_sync = 8 khz f8o aligned c8o
zl30102 data sheet 27 zarlink semiconductor inc. figure 18 - clock redundancy wi th two independent timing cards the following is an example of how ac tive/redundant setup can be configured. the active timing card is set based on the desired application and is set to: ? primary master mode, sec_mstr=0 ? normal mode, mode_sel1:0=00 (forces device to the input reference set at ref_sel) ? automatic mode, mode_sel1:0=11 (allows device to auto-switch if reference fails) the holdover and ref_fail pins help evaluate quality of clocks and quality of redundant clock. the redundant timing card is set based on desired applications and is set to: ? normal (manual) mode, mode_sel1:0=00 ? ref2 and ref2_sync as the input reference, ref_sel1=1 (forces redundant device to lock to output of active card) ? secondary master mode, sec_mstr=1 the holdover and ref_fail pins help evaluate quality of clocks and quality of redundant clock. active timing card osc zl30102 bits 0 clock bits 1 clock output clocks redundant timing card osc zl30102 output clocks active clock redundant clock ref0 ref1 ref2 ref2_sync ref2 ref2_sync active frame sync (optional) redundant frame sync (optional) mode_sel1:0=00 ref_sel1:0=10 sec_mstr=1 mode_sel1:0=11 ref_sel1:0=10 sec_mstr=0 bits 0 clock bits 1 clock ref0 ref1
zl30102 data sheet 28 zarlink semiconductor inc. when the redundant timing card is switched to becoming t he active timing card, the system controller should do the following: ? select primary master mode, sec_mstr=0 ? select automatic mode, mode_sel1:0=11 the new active timing card will automatically select a va lid input reference ref0 or ref1. if both input references are available and valid, t hen ref0 will be chosen over ref1. if the new active timing card should use the same input reference (ref0 or ref1) as the old active timing card used before it failed, the system controller should do the following instead: ? select holdover (manual) mode, mode_sel1:0=01 ? select primary master mode, sec_mstr=0 ? select the required reference (ref0 or ref1) as the input reference ? normal mode, mode_sel1:0=00 (forces device to the input reference set at ref_sel) ? select automatic mode, mode_sel1:0=11 it is recommended to maintain hms=1 when switching fr om redundant to active through the holdover mode, to eliminate output phase transients. when the active timing card is switched to becoming t he redundant timing card, the system controller should do the following: ? select normal (manual) mode, mode_sel1:0=00 ? select secondary master mode, sec_mstr=1 ? select ref2 and ref2_sync as the input reference, ref_sel1=1 the zl30102 allows for the switch from secondary master mode to primary master mode with no frequency or phase hits on the output clocks. the sw itch from primary master mode to se condary master mode may introduce a phase transient on the output clocks as the tie correction circuit is disabled to allow the secondary master device to track the active clocks closely.
zl30102 data sheet 29 zarlink semiconductor inc. 4.0 measures of performance the following are some pll performance indi cators and their corresponding definitions. 4.1 jitter timing jitter is defined as the high frequency variation of the clock edges from their ideal positions in time. wander is defined as the low-frequency variation of the clock e dges from their ideal positions in time. high and low frequency variation imply phase oscillation frequencies re lative to some demarcation frequency. (often 10 hz or 20 hz for ds1 or e1, higher for sonet/sdh clocks.) jitter parameters given in this data sheet are total timing jitter numbers, not cycle-to-cycle jitter. 4.2 jitter generation (intrinsic jitter) jitter generation is the measure of the jitter produced by the pll and is measured at its output. it is measured by applying a reference signal with no jitter to the input of the device, and measuring its output jitter. jitter generation may also be measured when the device is in a non-synchr onizing mode, such as free running or holdover, by measuring the output jitter of the dev ice. jitter is usually measured wi th various bandlimiting filters depending on the applicable standards. 4.3 jitter tolerance jitter tolerance is a measure of the ability of a pll to oper ate properly (i.e., remain in lock and or regain lock in the presence of large jitter magnitudes at various jitter frequencie s) when jitter is applied to its reference. the applied jitter magnitude and jitter frequency depends on the applicable standards. 4.4 jitter transfer jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter at the input of the device. i nput jitter is applied at va rious amplitudes and frequencies, and output jitter is measured with various filters depending on the applicable standards. for the zarlink digital plls two inter nal elements determine the jitter attenuat ion; the internal low pass loop filter and the phase slope limiter. the phase slope limiter limits the output phase slope to, for example, 61 s/s. therefore, if the input signal exceeds this rate, such as for very large amplitude low frequency input jitter, the maximum output phase slope will be limited (i.e ., attenuated). since intrinsic jitter is always present, jitter attenuation will appear to be lowe r for small input jitter signals than for large ones. consequently, accurate jitter transfer functi on measurements are usually made with large input jitter signals (for example 75% of the spec ified maximum tolerable input jitter). 4.5 frequency accuracy the frequency accuracy is defined as the absolute accuracy of an output clock signal when it is not locked to an external reference, but is operating in a free running mode. 4.6 holdover accuracy holdover accuracy is defined as the absolute accuracy of an output clock signal, when it is not locked to an external reference signal, but is operating using storage techniques . for the zl30102, the stora ge value is determined while the device is in normal mode and locked to an external reference signal.
zl30102 data sheet 30 zarlink semiconductor inc. 4.7 pull-in range also referred to as capture range. this is the input freq uency range over which the pll must be able to pull into synchronization. 4.8 lock range this is the input frequency range ov er which the synchronizer must be able to maintain synchronization. 4.9 phase slope phase slope is measured in seconds per second and is the rate at which a given signal changes phase with respect to an ideal signal. the given signal is typically the output signal. the ideal signal is of constant frequency and is nominally equal to the value of the final output signal or final input signal. anot her way of specifying the phase slope is as the fractional change per time un it. for example; a phase slope of 61 s/s can also be specified as 61 ppm. 4.10 time interval error (tie) tie is the time delay between a given ti ming signal and an ideal timing signal. 4.11 maximum time interval error (mtie) mtie is the maximum peak to peak delay between a give n timing signal and an ideal timing signal within a particular observation period. 4.12 phase continuity phase continuity is the phase difference between a given timi ng signal and an ideal timing signal at the end of a particular observation period. usually, the given timing signal and the ideal timing signal are of the same frequency. phase continuity applies to the output of the pll after a signal disturbance due to a reference switch or a mode change. the observation period is usually t he time from the disturbance, to just after the synchronizer has settled to a steady state. 4.13 lock time this is the time it takes the pll to frequency lock to t he input signal. phase lock occurs when the input signal and output signal are aligned in phase with respect to each othe r within a certain phase distance (not including jitter). lock time is affected by many factors which include: ? initial input to output phase difference ? initial input to output frequency difference ? pll loop filter bandwidth ? pll phase slope limiter ? in-lock phase distance the presence of input jitter makes it difficult to define when the pll is locked as it may not be able to align its output to the input within the required phase distance, dependen t on the pll bandwidth and the input jitter amplitude and frequency. although a short lock time is desirable, it is not always possible to achiev e due to other synchronizer requirements. for instance, better jitter transfer performance is achi eved with a lower frequency loop filter which increases lock time. and better (smaller) phase slope performa nce (limiter) results in longer lock times.
zl30102 data sheet 31 zarlink semiconductor inc. 5.0 applications this section contains zl30102 application specific details for power supply decoupling, reset operation, clock and crystal operation. 5.1 power supply decoupling it is recommended to place a 100 nf decoupling capacitor close to each pair of power and ground pins as illustrated in figure 19 to ensure optimal jitter performance. figure 19 - recommended power supply decoupling 5.2 master clock the zl30102 can use either a clock or cr ystal as the master timing source. za rlink application note zlan-68 lists a number of applicable osc illators and crystal s that can be used with the zl30102. 100 nf 33 agnd 36 av dd 25 v dd 61 v dd 37 av dd v core 12 av core 35 gnd 1 av core 14 1.8 v 3.3 v 44 av dd 45 av dd 100 nf 100 nf 100 nf 29 av dd 41 agnd 51 agnd 23 gnd zl30102 100 nf 100 nf gnd 13 v core 2 100 nf 1 gnd 100 nf 100 nf 40 gnd 34 gnd 100 nf 100 nf
zl30102 data sheet 32 zarlink semiconductor inc. 5.2.1 clock oscillator when selecting a clock oscillator, numerous parameters must be considered. this includes absolute frequency, frequency change over temperature, output rise and fa ll times, output levels, duty cycle and phase noise. the output clock should be connected directly (not ac co upled) to the osci input of the zl30102, and the osco output should be left open as shown in figure 20. figure 20 - clock oscillator circuit 5.2.2 crystal oscillator alternatively, a crystal oscillator may be used. a complete oscillator circuit made up of a crystal, resistor and capacitors is shown in figure 21. the accuracy of a crystal oscillator depends on the cryst al tolerance as well as the load capacitance tolerance. typically, for a 20 mhz crystal specified with a 32 pf load capacitance, each 1 pf change in load capacitance contributes approximately 9 ppm to the frequency deviation. consequent ly, capacitor tolerances and stray capacitances have a major effect on the accuracy of the oscillator frequency. the crystal should be a fundamental mode type - not an over tone. the fundamental mode crystal permits a simpler oscillator circuit with no additional filter components and is less likely to generate spurious responses. a typical crystal oscillator specification and circuit is shown in table 8 and figure 21 respectively. . 1 frequency 20 mhz 2 tolerance as required 3 rise & fall time < 10 ns 4 duty cycle 40% to 60% table 7 - typical clock oscillator specification 1 frequency 20 mhz 2 tolerance as required 3 oscillation mode fundamental 4 resonance mode parallel 5 load capacitance as required 6 maximum series resistance 50 ? table 8 - typical crystal oscillator specification +3.3 v 20 mhz out gnd 0.1 f +3.3 v osco zl30102 osci no connection
zl30102 data sheet 33 zarlink semiconductor inc. figure 21 - crystal oscillator circuit 5.3 power up sequence the zl30102 requires that the 3.3 v is not powered after the 1. 8 v. this is to prevent the risk of latch-up due to the presence of parasitic diodes in the io pads. two options are given: 1. power-up 3.3 v first, 1.8 v later 2. power up 3.3 v and 1.8 v simultaneously ensuring that the 3.3 v power is never lower than 1.8 v minus a few hundred millivolts (e.g., by using a schottky diode or controlled slew rate) 5.4 reset circuit a simple power up reset circuit with about a 60 s reset low time is shown in figure 22. resistor r p is for protection only and limits current into the rst pin during power down conditions. the re set low time is not critical but should be greater than 300 ns. figure 22 - power-up reset circuit osco 1 m ? 20 mhz zl30102 osci 100 ? 1 h the 100 ? resistor and the 1 h inductor may improve stability and are optional. +3.3 v rst r p 1 k ? c 10 nf r 10 k ? zl30102
zl30102 data sheet 34 zarlink semiconductor inc. 5.5 clock redundancy system architecture carrier-class telecommunications equipment deplo yed in today?s networks guarantee better than 99.999% operational availability (equivalent to less than 7 minute s of downtime per year). this high level of uninterrupted service is achieved by fully redundant architecture s with hot swappable cards like an ectf h.110 compliant system. timing for these types of systems can be gener ated by the zl30102 which supports primary/secondary master timing protection switching. the architecture shown in figure 23 is based on the zl30102 being deployed on two separate timing cards; the primary master timing card and the sec ondary master timing card. in normal operation the prim ary master timing card receives synchronization from the network and provides timing for the whole system. the redundant secondary master timing card is phase locked to t he backplane clock and frame pulse through its ref2 and ref2_sync inputs. these two designated inputs allow th e secondary master timing card to track the primary master timing card clocks with minimal phase skew. when the primary master timing ca rd fails unexpectedly (this failure is not related to refer ence failure) then all sw itch cards or line cards will detect this failure and they will switch to the timing supplied by the secondary master timing ca rd. the secondary master timing card will be promoted to primary master and switch from using the ref2 and re f2_sync inputs to one of the ref0 or ref1 inputs. figure 23 - typical clocking arch itecture of an ectf h.110 system zl30102 ref2 ref0 primary master timing card ref1 backplane ref2_sync c8o f8o ct_c8_a ct_frame_a ct_c8_b ct_frame_b ct_netref_1 ct_netref_2 sec_mstr master/slave control 0 zl30102 ref2 ref0 secondary master timing card ref1 ref2_sync c8o f8o sec_mstr master/slave control 1 switch card or line card switch card or line card
zl30102 data sheet 35 zarlink semiconductor inc. 6.0 characteristics 6.1 ac and dc electr ical characteristics * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. * voltages are with respect to ground (gnd) unless otherwise stated. * voltages are with respect to ground (gnd) unless otherwise stated. absolute maximum ratings* parameter symbol min. max. units 1 supply voltage v dd_r -0.5 4.6 v 2 core supply voltage v core_r -0.5 2.5 v 3 voltage on any digital pin v pin -0.5 6 v 4 voltage on osci and osco pin v osc -0.3 v dd + 0.3 v 5 current on any pin i pin 30 ma 6 storage temperature t st -55 125 c 7 tqfp 64 pin package power dissipation p pd 500 mw 8esd rating v esd 2kv recommended operating conditions* characteristics sym. min. typ. max. units 1 supply voltage v dd 2.97 3.30 3.63 v 2 core supply voltage v core 1.62 1.80 1.97 v 3 operating temperature t a -40 25 85 c dc electrical ch aracteristics* characteristics sym. min. max. units notes 1 supply current with: osci = 0 v i dds 19ma outputs loaded with 30 pf 2 osci = clock, out_sel=0 i dd 30 50 ma 3 osci = clock, out_sel=1 i dd 41 63 ma 4 core supply current with: osci = 0 v i cores 030 a 5osci = clocki core 14 20 ma 6 schmitt trigger low to high threshold point v t+ 1.47 1.5 v all device inputs are schmitt trigger type. 7 schmitt trigger high to low threshold point v t- 0.89 0.95 v 8 input leakage current i il -105 105 av i = v dd or 0 v 9 high-level output voltage v oh 2.4 v i oh = 8 ma for clock and frame-pulse outputs, 4 ma for status outputs
zl30102 data sheet 36 zarlink semiconductor inc. * supply voltage and operating temperature are as per recommended operating conditions. * voltages are with respect to ground (gnd) unless otherwise stated. * supply voltage and operating temperature are as per recommended operating conditions. * voltages are with respect to ground (gnd) unless otherwise stated. figure 24 - timing parameter measurement voltage levels * supply voltage and operating temperature are as per recommended operating conditions. * period min/max values are the limits to avoid a single-cycle fault detection. short-term and long-term average periods must b e within out-of- range limits. 10 low-level output voltage v ol 0.4 v i ol = 8 ma for clock and frame-pulse outputs, 4 ma for status outputs ac electrical charact eristics* - timing parameter measurem ent voltage levels (see figure 24). characteristics sym. cmos units 1 threshold voltage v t 0.5 v dd v 2 rise and fall threshold voltage high v hm 0.7 v dd v 3 rise and fall threshold voltage low v lm 0.3 v dd v ac electrical characteristi cs* - input timing for ref0, ref1 and ref2 references (see figure 25). characteristics symbol min. typ. max. units 1 8 khz reference period t ref8kp 121 125 128 s 2 1.544 mhz reference period t ref1.5p 338 648 950 ns 3 2.048 mhz reference period t ref2p 263 488 712 ns 4 8.192 mhz reference period t ref8p 63 122 175 ns 5 16.384 mhz reference period t ref16p 38 61 75 ns 6 reference pulse width high or low t refw 15 ns dc electrical ch aracteristics* characteristics sym. min. max. units notes t irf, t orf timing reference points all signals v hm v t v lm t irf, t orf
zl30102 data sheet 37 zarlink semiconductor inc. figure 25 - ref0/1/2 input timi ng and input to output timing * supply voltage and operating temperature are as per recommended operating conditions. * see figure 17, ?examples of ref2 & ref2_sync to output alignment? on page 26 for further explanation. figure 26 - ref2_sync timing ac electrical characteristi cs* - input timing for ref2_sync (see figure 26). characteristics symbol min. max. units notes 1 ref2_sync lead time t sync_ld 12 ns 2 ref2_sync lag time t sync_lg t refp - 28 ns t refp = minimum period of ref2 clock 3 ref2_sync pulse width high or low t sync_w 15 ns ref0/1/2 t refp t ref8kd , t ref_f8d t refw t refd t refw f8_32o output clock with the same frequency as ref ref2 ref2_sync t sync_ld t sync_lg t sync_w t refp edge used for alignment note: ref2 can be 1.544 mhz, 2.048 mhz, 8.192 mhz or 16.384 mhz. ref2_sync is 8 khz.
zl30102 data sheet 38 zarlink semiconductor inc. * supply voltage and operating temperature are as per recommended operating conditions. ac electrical characteristi cs* - input to output timing for ref0, ref1 and ref2 references when tie_clr = 0 (see figure 25). characteristics symbol min. max. units 1 8 khz reference input to f8/f32o delay t ref8kd -2.0 -0.3 ns 2 1.544 mhz reference input to c1.5o delay t ref1.5d -0.9 -0.2 ns 3 1.544 mhz reference input to f8/f32o delay t ref1.5_f8d -0.5 0.5 ns 4 2.048 mhz reference input to c2o delay t ref2d -1.1 -0.2 ns 5 2.048 mhz reference input to f8/f32o delay t ref2_f8d -0.2 0.6 ns 6 8.192 mhz reference input to c8o delay t ref8d -1.5 -0.5 ns 7 8.192 mhz reference input to f8/f32o delay t ref8_f8d -0.1 1.2 ns 8 16.384 mhz reference input to c16o delay t ref16d -1.1 1.9 ns 9 16.384 mhz reference input to f8/f32o delay t ref16_f8d 29.4 30.3 ns
zl30102 data sheet 39 zarlink semiconductor inc. * supply voltage and operating temperature are as per recommended operating conditions. ac electrical char acteristics* - e1 output timing (see figure 27). characteristics sym. min. max. units notes 1 c2o delay t c2d -0.4 0.3 ns outputs loaded with 30 pf 2 c2o pulse width low t c2l 243.2 244.1 ns 3f4o pulse width low t f4l 243.5 244.2 ns 4f4o delay t f4d 121.5 122.2 ns 5c4o pulse width low t c4l 121.1 122.3 ns 6c4o delay t c4d -0.3 1.1 ns 7 f8o pulse width high t f8h 121.6 123.2 ns 8 c8o pulse width low t c8l 60.3 61.3 ns 9 c8o delay t c8d -0.4 0.3 ns 10 f16o pulse with low t f16l 61.1 60.6 ns 11 f16o delay t f16d 29.9 30.8 ns 12 c16o pulse width low t c16l 28.7 30.8 ns 13 c16o delay t c16d -0.5 1.5 ns 14 f32o pulse width high t f32h 31.8 30.0 ns 15 c32o pulse width low t c32l 14.7 15.3 ns 16 c32o delay t c32d -0.5 0.5 ns 17 f65o pulse with low t f65l 15.4 14.8 ns 18 f65o delay t f65d 7.1 8.0 ns 19 c65o pulse width low t c65l 7.2 8.1 ns 20 c65o delay t c65d -1.0 1.0 ns 21 output clock and frame pulse rise time t or 1.1 2.0 ns 22 output clock and frame pulse fall time t of 1.2 2.3 ns
zl30102 data sheet 40 zarlink semiconductor inc. figure 27 - e1 output timing referenced to f8/f32o t f8h t f4d f4o c16o f8o t f16l f16o c8o c4o c2o t f16d t f4l t c16d t c8d t c4d t c16l t c8l t c4l t c2l t f32h c65o f32o t f65l f65o c32o t f65d t c65d t c32d t c65l t c32l f32o, c32o, f65o and c65o are drawn on a larger scale than the other waveforms in this diagram. t c2d
zl30102 data sheet 41 zarlink semiconductor inc. * supply voltage and operating temperature are as per recommended operating conditions. o figure 28 - ds1 output timing referenced to f8/f32o * supply voltage and operating temperature are as per recommended operating conditions. figure 29 - ds2 output timing referenced to f8/f32o ac electrical charact eristics* - ds1 output timing (see figure 28). characteristics sym. min. max. units notes 1 c1.5o delay t c1.5d -0.6 0.6 ns outputs loaded with 30 pf 2 c1.5o pulse width low t c1.5l 323.1 323.8 ns 3 c3o delay t c3d -0.7 0.5 ns 4 c3o pulse width low t c3l 161.1 162.0 ns 5 output clock and frame pulse rise time t or 1.1 2.0 ns 6 output clock and frame pulse fall time t of 1.2 2.3 ns ac electrical charact eristics* - ds2 output timing (see figure 29). characteristics sym. min. max. units notes 1 c6o delay t c6d -0.70 0.70 ns outputs loaded with 30 pf 2 c6o pulse width low t c6l 78.5 79.3 ns 3 output clock and frame pulse rise time t or 1.1 2.0 ns 4 output clock and frame pulse fall time t of 1.2 2.3 ns f8_32o t c1.5d t c1.5l c1.5o t c3d t c3l c3o f8_32o t c6d c6o t c6l
zl30102 data sheet 42 zarlink semiconductor inc. * supply voltage and operating temperature are as per recommended operating conditions. ac electrical characteristics* - osci 20mhz master clock input characteristics min. max. units notes 1 oscillator tolerance - ds1 -32 +32 ppm 2 oscillator tolerance - e1 -50 +50 ppm 3 duty cycle 40 60 % 4 rise time 10 ns 5 fall time 10 ns
zl30102 data sheet 43 zarlink semiconductor inc. 6.2 performance characteristics * supply voltage and operating temperature are as per recommended operating conditions. performance characteristics* - functional characteristics min. max. units notes 1 holdover accuracy 0.1 ppm 2 holdover stability 0 ppm determined by stability of the 20 mhz master clock oscillator 3 freerun accuracy 0 ppm determined by accuracy of the 20 mhz master clock oscillator 4 capture range -130 +130 ppm the 20 mhz master clock oscillator set at 0 ppm reference out of range threshold (including hysteresis) 5ds1 -64 -83 +64 +83 ppm the 20 mhz master clock oscillator set at 0 ppm 6e1 -100 -130 +100 +130 ppm the 20 mhz master clock oscillator set at 0 ppm lock time 7 1.8 hz filter 40 50 s 64 ppm to 100 ppm frequency offset, sec_mstr = 0, hms = 1, tie_clr = 1 and fastlock=0 8 58 hz filter (8 khz reference) 15 15 s 64 ppm to 100 ppm frequency offset, sec_mstr = 1, hms = 1, tie_clr = 1 and fastlock=0 9 922 hz filter 1 1 s 64 ppm to 100 ppm frequency offset, sec_mstr = 1, hms = 1, tie_clr = 1 and fastlock=0 10 fast lock 1 1 s 64 ppm to 100 ppm frequency offset and fastlock=1 output phase continuity (mtie) 11 reference switching 13 ns tie_clr =1 12 switching from normal mode to holdover mode 0ns 13 switching from holdover mode to normal mode 13 ns tie_clr =1 and hms=1 output phase slope 14 primary master mode 61 /s sec_mstr=0 15 secondary master mode 9.5 ms/s sec_mstr=1
zl30102 data sheet 44 zarlink semiconductor inc. * supply voltage and operating temperature are as per recommended operating conditions. * supply voltage and operating temperature are as per recommended operating conditions. * supply voltage and operating temperature are as per recommended operating conditions. * supply voltage and operating temperature are as per recommended operating conditions. performance characteristics*: input wande r and jitter tolerance conformance input reference frequency standard interface 1 1.544 mhz telcordia gr-1244-core ds1 line timing, ds1 external timing 2 2.048 mhz itu-t g.823 2048 kbit/s performance characteristics* : output jitter generation - ansi t1.403 conformance signal ansi t1.403 jitter generation requirements zl30102 maximum jitter generation units jitter measurement filter limit in ui equivalent limit in the time domain ds1 interface 1 c1.5o (1.544 mhz) 8 khz to 40 khz 0.07 ui pp 45.3 0.20 ns pp 2 10 hz to 40 khz 0.5 ui pp 324 0.23 ns pp performance characteristics* : output jitter generation - itu-t g.747 conformance signal itu-t g.747 jitter generation requirements zl30102 maximum jitter generation units jitter measurement filter limit in ui equivalent limit in the time domain ds2 interface 1 c6o (6.312 mhz) 10 khz to 60 khz 0.05 ui pp 7.92 0.13 ns pp performance characteristics* : output jitter generation - itu-t g.812 conformance signal itu-t g. 8 1 2 jitter generation requirements zl30102 maximum jitter generation units jitter measurement filter limit in ui equivalent limit in the time domain e1 interface 1 c2o (2.048 mhz) 20 hz to 100 khz 0.05 ui pp 24.4 0.26 ns pp
zl30102 data sheet 45 zarlink semiconductor inc. * supply voltage and operating temperature are as per recommended operating conditions. performance characteristics* - unfiltered jitter generation characteristics max. [ns pp ] notes 1 c1.5o (1.544 mhz) 0.42 2 c2o (2.048 mhz) 0.38 3 c3o (3.088 mhz) 0.53 4c4o (4.096 mhz) 0.30 5 c6o (6.312 mhz) 0.58 6 c8o (8.192 mhz) 0.22 7 c16o (16.384 mhz) 0.23 8 c32o (32.768 mhz) 0.20 9 c65o (65.536 mhz) 0.22 10 f4o (8 khz) 0.43 11 f8o (8 khz) 0.43 12 f16o (8 khz) 0.44 13 f32o (8 khz) 0.43 14 f65o (8 khz) 0.46
c zarlink semiconductor 2002 all rights reserved. apprd. issue date acn package code previous package codes
www.zarlink.com information relating to products and services furnished herein by zarlink semiconductor inc. or its subsidiaries (collectively ?zarlink?) is believed to be reliable. however, zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from t he application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. neither the supply of such information or purchase of product or service conveys any license, either express or implied, u nder patents or other intellectual property rights owned by zarlink or licensed from third parties by zarlink, whatsoever. purchasers of products are also hereby notified that the use of product in certain ways or in combination with zarlink, or non-zarlink furnished goods or services may infringe patents or other intellect ual property rights owned by zarlink. this publication is issued to provide information only and (unless agreed by zarlink in writing) may not be used, applied or re produced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, t heir specifications, services and other information appearing in this publication are subject to change by zarlink without notice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user?s responsibility t o fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not b een superseded. manufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. all products and materials are sold and services provided subject to zarlink?s conditi ons of sale which are available on request. purchase of zarlink?s i 2 c components conveys a licence under the philips i 2 c patent rights to use these components in and i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright zarlink semiconductor inc. all rights reserved. technical documentation - not for resale for more information about all zarlink products visit our web site at

▲Up To Search▲

Price & Availability of ZL30102QDG

	To Download ZL30102QDG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .